By Rodnay Zaks
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If it is positive, no interrupt has been generated by the device and the program tests the next one, and so on. However, if the device is found to have generated an interrupt, a specific routine must then determine what to do next. Let us examine it. Identifying one out of 7 possible internal interrupts for the 6522 Referring to Fig 2-22, it can be seen that seven possible conditions may set an internal interrupt in the IFR register of the 6522: Tl, T2, CBl, CB2, SR, CAI, CA2. If all of the internal resources of the 6522 are used simultaneously, as is often the case, then all possibilities should be checked.
All El SHIFT - - \ m~~ no~~:-~1;;-1~r THE INPUT OUTPUT CHIPS The PIO Section The PIO Section provides two 8-bit bidirectional ports. Each port is equipped with an input/output register. They are called respectively ORA and ORB for port A and port B. They are shown on Fig 2-14. Each register is associated with a direction register, respectively DDRA AND DDRB. Whenever the corresponding bit of the data direction register is set to "l" the line connected to the OR will be an output. Whenever the data direction bit is "O", the corresponding line will be an input.
If bit 7 is "I", each "I" written into IER will set an enable. Example: Let us enable CAI and CA2 interrupts, and disable all others (see Fig 2-28): LDA #$7C STA LDA IER #$83 STA IER "01111100" 2 TO 6 CLEAR BITS "10000011" 0 AND 1 ENABLE BITS Exercise 2-1: Write a program to enable CBJ interrupts, and disable others. Exercise 2-2: Disable CBJ and CB2, leaving others unchanged. , whenever several bits of the IFR are used, the program will have to check the contents of IFR and determine which interrupt has occurred.
6502 Applications Book by Rodnay Zaks